I/O buffer with variable conductivity

ABSTRACT

A driver structure for an I/O buffer circuit is disclosed. The driver structure includes a pre-push-pull driver and a post-push-pull driver. A delay circuit along is connected in series between the input signals of the pre-push-pull driver and the post-push-pull driver. After a delay time following a transition of the input signal, the circuit operation of the post-push-pull driver is turned off before the amplitude of the output signal reaches its maximum overshooting. This changes the output conductivity to inhibit the overshooting in the output signal, preventing power bounce and ground bounce at the receiving end.

BACKGROUND OF THE INVENTION

[0001] 1. Field of Invention

[0002] The invention relates to an I/O (Input/Output) buffer circuit.More particular, the invention pertains to an I/O buffer circuit withvariable conductivity, which can improve the data integrity and decreasesignal wave deformation during SSO (Simultaneous Switching Output).

[0003] 2. Related Art

[0004] With reference to FIG. 1, the conventional I/O buffer circuit isa push-pull driver comprised of a PMOS (P-type Metal OxideSemiconductor) transistor T1 and an NMOS (N-type Metal OxideSemiconductor) transistor T2. The transistors T1 and T2 are connectedbetween a work voltage V_(dd) and the ground Gnd in series. The inputsignal V_(i) passes through two NOT gates 13 to reach the gates of thetransistors T1 and T2. The drains of the transistors T1 and T2 are bothconnected to the output terminal pad, output signal V_(o). When theinput signal V_(i) has a Hi voltage, it is inverted by the NOT gate 13into a Lo voltage. The transistor T1 called a pull-up transistor becomesconductive while the transistor T2 cuts off. The output signal V_(o) isthus Hi voltage. On the contrary, when the input signal V_(i) has a Lovoltage, the transistor T2 called a pull-down transistor becomesconductive while the transistor T1 cuts off. Therefore, the outputsignal V_(o) is Lo voltage.

[0005] In a VLSI (Very Large Scale Integrated) circuit, the so-calledSSO refers to the simultaneous transition of the output signals from twoor more I/O buffers. When the SSO appears, the internal power Vdd′ andthe ground Gnd′ of the VLSI circuit may produce power bounce and groundbounce. Such noise signal produced by the SSO will cause incorrectjudgment on data levels by the receiver. The power bounce and groundbounce often result from simultaneous transitions on a plurality ofoutput signals of the I/O buffers from Hi to Lo or vice versa. FIG. 2shows an equivalent circuit of a VLSI internal I/O buffer bus. As shownin the drawing, the internal power Vdd′ and the ground Gnd′ of the VLSIcircuit are connected with an external power V_(dd) and an externalground Gnd through protector inductors L₁ and L₂, respectively. In theI/O buffer bus, one I/O port D1 is maintained at Hi while another I/Oport D2 at Lo. The rest of I/O ports may have Hi level or Lo level. Whenthe SSO occurs, the internal power Vdd′ and the ground Gnd′ willgenerate a larger load current i. When the load current flows throughthe inductors L₁ and L₂, the outputs Hi level V^(dd) and Lo level Gndfrom the I/O ports D1 and D2 become unstable due to power bounce andground bounce caused by the voltage drops of the inductors L₁ and L₂,affecting the accuracy of data reception.

[0006] Let's further explain the power bounce phenomenon occurring tothe I/O port D1 with reference to FIG. 3A. It shows an equivalentcircuit of the I/O port D1 in FIG. 2 and the signal waveform at thereceiving end. When the input signals of the rest of I/O port bus changefrom Lo to Hi, the internal power Vdd′ of the VLSI circuit has a loadcurrent i1 going to the receiving end. This load current produces avoltage drop L₁(di1/dt) on the inductor L1, so that the Hi level V_(dd)of the I/O port D1 produces a maximal undershooting oscillation (asshown on the right-hand side of FIG. 3A). In response to thisphenomenon, the voltage R_(A) at the receiving end also drops.Therefore, the voltage level at the receiving end may be determinedincorrectly as Lo instead of Hi. Such incorrect determinations andactions will affect the normal operations of the circuit.

[0007] We use FIG. 3B to further explain the ground bounce phenomenonoccurring to the I/O port D2. It shows an equivalent circuit of the I/Oport D2 in FIG. 2 and the signal waveform at the receiving end. When theinput signals of the rest of I/O port bus change from Hi to Lo, theinternal ground Gnd′ of the VLSI circuit draws a load current i2 fromthe receiving end. This load current produces a voltage increaseL₂(di2/dt) on the inductor L₂, making the I/O port D2 outputs a Lo levelvoltage (as shown on the right-hand side of FIG. 3B). In response tothis phenomenon, the voltage R_(B) at the receiving end produces abounce. Therefore, the voltage level at the receiving end may bedetermined incorrectly as Hi instead of Lo. Such incorrectdeterminations and actions also affect the normal operations of thecircuit.

SUMMARY OF THE INVENTION

[0008] A objective of the invention provides an I/O buffer circuit withvariable conductivity. Through the conductivity change of the buffercircuit, the output signals from the I/O ports to avoid maximalovershooting and ringback oscillations during transitions.

[0009] In observation of the unstable phenomena occurred to the receiveend during the SSO transitions that may result in incorrect actions ofcircuit operations, the invention thus improves the I/O buffer drivercircuit. The invention uses a delay circuit in combination with a CMOStransistor driver to change the conductivity characteristic of theoutput signals. When the I/O output signals make transitions, theconductivity of the CMOS transistor first increases. Before the outputsignal wave reaches its maximum overshooting, the conductivity isgradually lowered. This can effectively inhibit the maximum overshootingphenomena of the output signals. Accordingly, power bounce and groundbounce can be avoided at the receiving end. The invention can furtherimprove the data accuracy and integrity during SSO.

[0010] In an embodiment of the invention, the I/O buffer circuit has anoutput signal that includes a pre-push-pull driver and a post-push-pulldriver. In particular, a delay circuit in combination with a simplelogic circuit is connected between the pre-push-pull driver and thepost-push-pull driver in series. After a delay time following thetransition of input signal, the post-push-pull driver operation is shutdown before the amplitude of the output signal reaches its maximumovershooting so as to change the conductivity of the output.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention will become more fully understood from thedetailed description given hereinbelow illustration only, and thus arenot limitative of the present invention, and wherein:

[0012]FIG. 1 is a conventional I/O buffer circuit;

[0013]FIG. 2 shows an equivalent circuit of an internal I/O buffer busof a semiconductor IC;

[0014]FIG. 3A shows an equivalent circuit of the I/O port D1 in FIG. 2and the signal waveform at the receiving end;

[0015]FIG. 3B shows an equivalent circuit of the I/O port D2 in FIG. 2and the signal waveform at the receiving end;

[0016]FIG. 4 is a circuit diagram of the disclosed I/O buffer withvariable conductivity of the present invention; and

[0017]FIG. 5 shows the signal waveforms at various points in FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

[0018] With reference to FIG. 4, the I/O buffer with variableconductivity of the present invention includes a pre-push-pull driver 1and a post-push-pull driver 2. The input signals of pre-push-pull driver1 and the post-push-pull driver 2 are connected with a delay circuit 3in series, so that the two input signals have a delayed phasedifference. The pre-push-pull driver 1 and post-push-pull driver 2 drivethe output signal V_(o) in the delayed phase difference to provide thedesired variable conductivity.

[0019] When the input signal V_(i) makes a transition, the pre-push-pulldrive 1 and post-push-pull driver 2 simultaneously drive the outputsignal V_(o) to provide larger conductivity. Due to the effect of thedelay circuit 3, the post-push-pull driver 2 stops driving after a delaytime following the transition of the input signal V_(i). Theconductivity of the output signal V_(o) is thus changed to provide asmaller conductivity, inhibiting the increase of the load current i andpreventing the overshooting of the output signal V_(o). Therefore, whenthe I/O buffer of the present invention has SSO, no power bounce andground bounce will happen to the output signal V_(o) at the receivingend and the data accuracy and integrity during SSO can be improved.

[0020] The I/O buffer with variable conductivity of the presentinvention utilizes a delay circuit 3, logic gates NAND 11, NOR 12, andfour NOT gates (131,132,133,134). The I/O buffer makes thepost-push-pull driver 2 conductive during the transition of the inputsignal V_(i). After a delay time (determined by the delay circuit 3),the post-push-pull driver 2 stops driving. The operation of the circuitis described in the following paragraphs.

[0021] When the input signal V_(i) changes from Lo to Hi and is invertedby the NOT 131 and 132, the pull-up transistor T1 of the pre-push-pulldriver 1 is conductive while the pull-down transistor T2 being cut off.At the same time, the output signal of the delay circuit 3 has not madea transition and is kept at Lo due to the delay effect. The outputsignal of the delay circuit 3 passes through the NOT 133 and the NAND 11to reach the gate of the transistor T3. The pull-up transistor T3 of thepost-push-pull driver 2 becomes conductive. The output signal of thedelay circuit 3 passes through the NOT 134 and the NOR 12 to reach thegate of the transistor T4. the pull-down transistor T4 of thepost-push-pull driver 2 is cut off. Therefore, when the input signalV_(i) changes from Lo to Hi, the pull-up transistors T1, T3 of thepre-push-pull drivers 1 and post-push-pull drivers 2 become conductive,providing a load current i with desired pull-up conductivity to theoutput signal V_(o).

[0022] After a delay time and before the load current i increases to itsmaximum overshooting, the output signal of the delay circuit 3 changesfrom Lo to Hi. After the output signal of the delay circuit 3 passesthrough the NOT 133 and the NAND 11, the pull-up transistor T3 of thepost-push-pull driver 2 is cut off. After the output signal of the delaycircuit 3 passes through the NOT 134 and the NOR 12, the pull-downtransistor T4 of the post-push-pull driver 2 is kept off. Therefore, thepull-up conductivity of the output signal V_(o) is changed so that thepull-up conductivity drops. This thus prevents the load current i frommaximal overshooting and ringback oscillations.

[0023] When the input signal V_(i) changes from Hi to Lo and is invertedby the NOT 131 and 132, the pull-up transistor T1 of the pre-push-pulldriver 1 is cut off while the pull-down transistor T2 being conductive.At the same time, the output signal of the delay circuit 3 has not madea transition and is kept at Hi due to the delay effect. After the outputsignal of the delay circuit 3 passes through the NOT 134 and the NOR 12,the pull-down transistor T4 of the post-push-pull driver 2 becomesconductive. After the output signal of the delay circuit 3 passesthrough the NOT 133 and the NAND 11, the pull-up transistor T3 of thepost-push-pull driver 2 is cut off. Therefore, when the input signalV_(i) changes from Hi to Lo, the pull-down transistors T2, T4 of thepre-push-pull driver 1 and post-push-pull driver 2 become conductive,providing a load current i with pull-up conductivity to the outputsignal V_(o).

[0024] After a delay time and before the load current i increases to itsmaximum overshooting, the output signal of the delay circuit 3 changesfrom Hi to Lo. After the output signal of the delay circuit 3 passesthrough the NOT 134 and the NOR 12, the pull-down transistor T4 of thepost-push-pull driver 2 is cut off. After the output signal of the delaycircuit 3 passes through the NOT 133 and the NAND 11, the pull-uptransistor T3 of the post-push-pull driver 2 is kept off. Therefore, thepull-down conductivity of the output signal V_(o) is changed so that thepull-down conductivity drops. This thus prevents the load current i frommaximal undershooting and ringback oscillations.

[0025] In FIG. 5, thin lines are waveforms on various signals in theprior art. The output signal V_(o) depicted by thin line has theproblems of overshooting and ringbacks. Thick lines are produced by thedisclosed circuit of the present invention. the output signal V_(o)depicted by thick line does not have either overshooting or ringbacks.This is because the invention can effectively inhibit the overshootingand ringbacks due to SSO.

[0026] With reference to FIG. 4, when the input signal V_(i) changesfrom Lo to Hi, the input signal of the post-push-pull driver 2 isdelayed for a period due to the delay circuit. The output signal of thedelay circuit goes through some simple logic operations, turning on thetransistor T1 while turning off the transistors T2 and T4. Thetransistor T3 is on for a period of time Δt and then off, so that theload current i changes the pull-up conductivity thereof due to thetransistor T3 being cut off. The load current i is thus inhibitedwithout producing overshooting. The pull-up conductivity in the outputsignal V_(o) then slowly drops. The pull-up transistor T1 of thepre-push-pull driver 1 takes over to supply the conductivity of theoutput signal, so that the I/O buffer bus does not cause power bounce atthe receiving end during SSO.

[0027] When the input signal V_(i) changes from Hi to Lo, the inputsignal of the post-push-pull driver 2 is delayed for a period due to thedelay circuit. The output signal of the delay circuit goes through somesimple logic operations, turning on the transistor T2 while turning offthe transistors T1 and T3. The transistor T4 is on for a period of timeΔt and then off, so that the load current i changes its pull-downconductivity due to the transistor T4 being cut off. The load current iis thus inhibited without producing undershooting. The pull-upconductivity in the output signal V_(o) then slowly increases. Thepull-down transistor T2 of the pre-push-pull driver 1 takes over tosupply the conductivity of the output signal, so that the I/O buffer busdoes not cause ground bounce at the receiving end during SSO.

EFFECTS OF THE INVENTION

[0028] The invention provides an I/O buffer with variable conductivity.Using a driver structure with the combination of a delay circuit andCMOS transistors, the conductivity of the output signal can be changedto avoid signal bounces and ringbacks. Therefore, the disclosed drivercan be widely used in the I/O buffers for VLSI circuits to preventunstable signal outputs caused by transitions during SSO.

[0029] Although the invention has been described with reference tospecific embodiments, this description is not meant to be construed in alimiting sense. Various modifications of the disclosed embodiments, aswell as alternative embodiments, will be apparent to persons skilled inthe art. It is, therefore, contemplated that the appended claims willcover all modifications that fall within the true scope of theinvention.

[0030] While the invention has been described by way of example and interms of the preferred embodiment, it is to be understood that theinvention is not limited to the disclosed embodiments. To the contrary,it is intended to cover various modifications and similar arrangementsas would be apparent to those skilled in the art. Therefore, the scopeof the appended claims should be accorded the broadest interpretation soas to encompass all such modifications and similar arrangements. Forexample, an I/O buffer circuit of the present invention, comprising: apre-driver, at least one post-driver, and a delay circuit, wherein thedelay circuit is connected in series between the input signals of thepre-driver and the post-drivers to turn off the operation of thepost-driver after the pre-driver and the post-driver work for a delaytime.

What is claimed is:
 1. An I/O buffer circuit having an input signal andan output signal, comprising: a pre-driver consisting of semiconductorswitches; a post-driver consisting of semiconductor switches; and adelay circuit to turn off the operation of the post-driver after a delaytime following a transition of the input signal, thus changing theconductivity of the output signal.
 2. The buffer circuit of claim 1,wherein said pre-driver and post-driver are push-pull drivers.
 3. Thebuffer circuit of claim 1, wherein said semiconductor switches are CMOStransistors.
 4. The buffer circuit of claim 1, wherein said delaycircuit turns off the operation of the post-driver after the delay timeand before the amplitude of the output signal reaches a maximumovershooting, thus changing the conductivity of the output signal. 5.The buffer circuit of claim 4, wherein said conductivity first increasesthen decreases.
 6. The buffer circuit of claim 1, wherein saidconductivity first increases then decreases
 7. The buffer circuit ofclaim 1, wherein said delay circuit includes a logic circuit.
 8. Thebuffer circuit of claim 1, wherein said delay circuit is connected inseries between the input signals of the pre-driver and the post-driver.9. An I/O buffer circuit comprising: a pre-driver, consisting of CMOStransistors; at least one post-driver, consisting of CMOS transistors;and a delay circuit, which is connected in series between the inputsignals of the pre-driver and the post-driver to turn off the operationof the post-driver after the pre-driver and the post-driver work for adelay time.
 10. The buffer circuit of claim 9, wherein said pre-driverand the post-driver are push-pull drivers.
 11. The buffer circuit ofclaim 9, wherein said delay circuit turns off the operation of thepost-driver after the delay time following a transition of the inputsignal, thus changing the conductivity of a circuit output.
 12. Thebuffer circuit of claim 11, wherein the delay circuit turns off theoperation of the post-driver after the delay time following thetransition and before the amplitude of a output signal reaches a maximumovershooting, thus changing the conductivity of the circuit output. 13.An I/O buffer circuit having an input signal and an output signal,comprising: multi-level drivers, each consisting of CMOS transistors;and a delay circuit, which turns off the operations of part of thedrivers after a delay time following a transition of the input signal,thus changing the conductivity of the output signal.
 14. The buffercircuit of claim 13, wherein said pre-driver and the post-driver arepush-pull drivers.
 15. The buffer circuit of claim 13, wherein saiddelay circuit turns off the operation of the post-driver after the delaytime following the transition and before the amplitude of the outputsignal reaches a maximum overshooting, thus changing the conductivity ofthe output signal.
 16. The buffer of claim 13, wherein said conductivityfirst increases then decreases.
 17. The buffer of claim 13, wherein saiddelay circuit includes a logic circuit.